(1) Field of the Invention
The present invention relates to an inspecting method, an inspecting apparatus, and a method of manufacturing semiconductor devices, and more particularly to a method of and an apparatus for inspecting samples such as wafers or the like for pattern defects, extraneous deposits, etc., and a method of manufacturing semiconductor devices, which includes a process of inspecting samples such as wafers or the like for pattern defects, extraneous deposits, etc.
(2) Description of the Related Art
In the field of the fabrication of semiconductor wafers, wafers are inspected at suitable stages for pattern defects, extraneous deposits, etc. (simply referred to as “defects”) in an effort to provide a stable supply of high-quality semiconductor products.
At present, there have been employed various processes for inspecting samples for defects. Those processes include a dark field (DF) process for irradiating a sample surface with a laser beam and detecting scattered light therefrom, a bright field (BF) process for irradiating a sample surface with light and detecting reflected light therefrom, and a scanning electron microscope (SEM) process for irradiating a sample surface with an electron beam and detecting secondary electrons emitted from the sample surface. Heretofore, there have also been proposed a process of comparing an SEM-generated sample image with a given reference image and detecting any image difference as a defect, and a process of comparing an SEM-generated sample image with a given standard range and detecting an image area out of the standard range as a defect (for details, reference should be made to Japanese laid-open patent publication No. 9-312318).
Still another inspection process is known as a voltage contrast (VC) process for observing an SEM image of a produced wiring pattern for a potential state thereof to check if it suffers electrical defects such as disconnections or the like.
Although each of the various inspection processes referred to above may be carried out alone, it may be combined with another inspection scheme for higher defect detecting accuracy. It has also been attempted to perform a defect source analysis (DSA) on the results of inspections in a plurality of steps of a semiconductor device fabrication process for identifying any fabrication step that is responsible for a defect. If such a defect-causing fabrication step can be hunted down, then it is possible to take an appropriate action to correct the fabrication step for a higher semiconductor device yield.
However, some problems arise out of the DSA as described below.
A DSA using the results of a DF or BF inspecting process performed prior to the formation of a wiring pattern and the results of a VC inspecting process subsequent to the formation of the wiring process will be described below.
FIG. 10 of the accompanying drawings is illustrative of a conventional DSA.
For forming a TEG (Test Element Group) 101 shaped as shown in FIG. 10 on a wafer 100, fabrication steps of film growth, photolithography, and etching are performed prior to the formation of a combtoothed wiring pattern 102 and isolated wiring patterns 103 according to the Damascene process. After these fabrication steps are carried out, a DF or BF inspecting process is performed. Then, a wiring material is embedded and a CMP (Chemical Mechanical Polishing) process is performed, after which a VC inspecting process is performed.
FIG. 10 shows that three defects 104a, 104b, 104c are detected by the inspecting process performed prior to the formation of the combtoothed wiring pattern 102 and the isolated wiring patterns 103. Of these defects 104a, 104b, 104c, the defect 104a is present in the combtoothed wiring pattern 102 that is finally produced, and the defects 104b, 104c are present in areas other than the combtoothed wiring pattern 102 and the isolated wiring patterns 103 that are finally produced.
In the VC inspecting process performed subsequent to the formation of the combtoothed wiring pattern 102 and the isolated wiring patterns 103, an area (referred to as a VC inspection area) 105 including areas of the combtoothed wiring pattern 102 near its tip ends is observed based on an SEM image thereof while a certain voltage is being applied to the combtoothed wiring pattern 102. Since the potential in an area of the combtoothed wiring pattern 102 which is suffering a disconnection and the potential in an area of the combtoothed wiring pattern 102 which is suffering no disconnection differ from each other, secondary electrons emitted from these different areas have different levels of energy. Consequently, the SEM image of the VC inspection area 105 has a certain contrast difference. The VC inspecting process checks if there is a disconnection or the like or not based on the contrast information of the SEM image.
The VC inspection area 105 does not necessarily require to contain a defect a disconnection or the like therein. Even if a disconnection or the like exists at the base of a tooth of the combtoothed wiring pattern 102, the defect shows its influence on the tooth from the base up to its tip end in the VC inspecting process. Specifically, as shown in FIG. 10, the area extending from the defect 104a in the tooth of the combtoothed wiring pattern 102 to the tip end thereof shows a different level of contrast than the other area, and represents a nonconductive area 106. Actually, the defect 104a has caused the nonconductive area 106 to occur, and the fabrication step which has produced the defect 104a is responsible for the nonconductive area 106. The fact will be made clear by a DSA.
For performing a DSA using the data from the defect inspection prior to the formation of the wiring patterns and the data from the VC inspection subsequent to the formation of the wiring patterns, a circular DSA area 107 is established around the center at the center O of gravity of a nonconductive area 106a that is present in the VC inspection area 105, based on the pattern data of the TEG 101, the circular DSA area 107 being large enough to cover a relatively wide range of the TEG 101. The circular DSA area 107 thus established, however, is likely to reduce the accuracy of the DSA.
Specifically, though only the defect 104a is actually responsible for the occurrence of the nonconductive area 106 in the example shown in FIG. 10, the DSA counts all the defects 104a, 104b, 104c that are present in the DSA area 107 as being responsible for the occurrence of the nonconductive area 106. Even if the defect 104a, i.e., a killer defect, and the defects 104b, 104c, i.e., non-killer defects, are produced in different fabrication steps, the fabrication steps which have actually caused only the non-killer defects to occur are regarded as fabrication steps that have produced killer defects. As a result, the defect-producing fabrication step cannot accurately be identified.
Furthermore, if all the defects 104a, 104b, 104c in the DSA area 107 are regarded as having caused the nonconductive area 106 regardless of the types of those defects 104a, 104b, 104c, then it may become impossible to determine whether the nonconductive area 106 has been caused by an extraneous deposit or a pattern void. This failure is applicable irrespective of whether the defects 104a, 104b, 104c in the DSA area 107 are produced in respective different fabrication steps or in the same fabrication step.